The present invention relates to a test circuit, an integrated circuit, and a test method.
Recently, as integrated circuits have become larger, attempts to detect faults (such as wiring defects or element defects) in the entire circuit comprising such integrated circuits have run into problems in that the test pattern has become more complicated, and thus the development of such a test pattern is taking longer and is more expensive. A test method called a scan method is known as a means of solving this problem, as disclosed in Japanese Patent Application Laid-Open No. 2001-183424.
With this scan method, after the logic design has been completed and a net list of the circuit has been created, scan flip-flops (scanner circuits) are inserted into the circuit (net list). More specifically, flip-flops (hereinafter abbreviated to FF) within the circuit are replaced by scan FFs. A net list of these scan FFs is then used to perform fault simulations and create (automatically generate) a text pattern. This test pattern is used to test trial products or mass-produced products.
However, even when this scan method is used, it is becoming difficult to create the test pattern and improve the fault detection rate with large-scale integrated circuits. In particular, a method of integrated circuit design that has recently become popular is to form circuits with specific functions into blocks, then connect together macro blocks (macro cells) that are circuit blocks formed in this manner. For example, it is possible to design an integrated circuit (ASIC) for a specific purpose involving the USB 2.0 function, by connecting together a macro block that conforms to the USB 2.0 Transceiver Macrocell Interface (UTMI) specification, a circuit (serial interface engine) that controls that UTMI block, and a user-customized circuit. In such a case, it is comparatively simple to create a test pattern for each of these macro blocks, but a technical problem occurs in that it is not simple to create a test pattern for detecting faults (wiring defects) in the connecting portions between the macro blocks.
A further technical problem is caused by the huge number of terminals (pins) involved with integrated circuits, making it necessary to reduce that number as far as possible. It is therefore preferable to minimize the number of test terminals as far as possible.